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cy7c1371d cy7c1373d 18-mbit (512 k 36/1 m 18) flow-through sram with nobl? architecture cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-05556 rev. *l revised october 5, 2012 18-mbit (512 k 36/1 m 18) flow-through sram with nobl? architecture features no bus latency ? (nobl ? ) architecture eliminates dead cycles between write and read cycles supports up to 133-mhz bus operations with zero wait states ? data is transferred on every clock pin-compatible and functionally equivalent to zbt? devices internally self-timed output buffe r control to eliminate the need to use oe registered inputs for flow through operation byte write capability 3.3 v/2.5 v i/o power supply (v ddq ) fast clock-to-output times ? 6.5 ns (for 133-mhz device) clock enable (cen ) pin to enable clock and suspend operation synchronous self-timed writes asynchronous output enable available in jedec-standard pb-free 100-pin tqfp, pb-free and non pb-free 119-ball bga, and 165-ball fbga packages three chip enables for simple depth expansion automatic power-down feature av ailable using zz mode or ce deselect ieee 1149.1 jtag-compatible boundary scan burst capability ? linear or interleaved burst order low standby power functional description the cy7c1371d/cy7c1373d is a 3.3 v, 512 k 36/1 m 18 synchronous flow through burst sram designed specifically to support unlimited true back-to-back read/write operations with no wait state insertion. the cy7c1371d/cy7c1373d is equipped with the advanced no bus latency (nobl) logic required to enable consecutive read/write operations with data being transferred on every clock cycle. this feature dramatically improves the throughput of data through the sram, especially in systems that require fre quent write-read transitions. all synchronous inputs pass through input registers controlled by the rising edge of the clock. the clock input is qualified by the clock enable (cen ) signal, which when deasserted suspends operation and extends the previous clock cycle. maximum access delay from the clock ri se is 6.5 ns (133-mhz device). write operations are controlled by the two or four byte write select (bw x ) and a write enable (we ) input. all writes are conducted with on-chip synchron ous self-timed write circuitry. three synchronous chip enables (ce 1 , ce 2 , ce 3 ) and an asynchronous output enable (oe ) provide for easy bank selection and output tristate cont rol. to avoid bus contention, the output drivers are synchronously tristated during the data portion of a write sequence. selection guide description 133 mhz 100 mhz unit maximum access time 6.5 8.5 ns maximum operating current 210 175 ma maximum cmos standby current 70 70 ma
cy7c1371d cy7c1373d document number: 38-05556 rev. *l page 2 of 37 logic block diagram ? cy7c1371d c mode bw a bw b we ce1 ce2 ce3 oe read logic dqs dqp a dqp b dqp c dqp d memory array e input register bw c bw d address register write registry and data coherency control logic burst logic a0' a1' d1 d0 q1 q0 a0 a1 adv/ld ce adv/ld c c lk c en write drivers d a t a s t e e r i n g s e n s e a m p s write address register a0, a1, a o u t p u t b u f f e r s e zz sleep control
cy7c1371d cy7c1373d document number: 38-05556 rev. *l page 3 of 37 logic block diagram ? cy7c1373d c mode bw a bw b we ce1 ce2 ce3 oe read logic dqs dqp a dqp b memory array e input register address register write registry and data coherency control logic burst logic a0' a1' d1 d0 q1 q0 a0 a1 adv/ld ce adv/ld c c lk c en write drivers d a t a s t e e r i n g s e n s e a m p s write address register a0, a1, a o u t p u t b u f f e r s e zz sleep control
cy7c1371d cy7c1373d document number: 38-05556 rev. *l page 4 of 37 contents pin configurations ........................................................... 5 pin definitions .................................................................. 9 functional overview ...................................................... 10 single read accesses .............................................. 10 burst read accesses ................................................ 10 single write accesses ............................................... 10 burst write accesses ................................................ 11 sleep mode ............................................................... 11 interleaved burst address tabl e ............................... 11 linear burst address table ....................................... 11 zz mode electrical characteri stics ............................ 11 truth table ...................................................................... 12 partial truth table for read/write ................................ 12 partial truth table for read/write ................................ 13 ieee 1149.1 serial boundary sc an (jtag) ... ........... .... 14 disabling the jtag feature ...................................... 14 test access port (tap) ............................................. 14 performing a tap r eset .......... .............. .......... 14 tap registers ...................................................... 14 tap instruction set ................................................... 14 tap controller state diagram ....................................... 16 tap controller block diagram ...................................... 17 tap timing ...................................................................... 17 tap ac switching characteristics ............................... 18 3.3 v tap ac test conditions ....................................... 19 3.3 v tap ac output load equivalent ......................... 19 2.5 v tap ac test conditions ....................................... 19 2.5 v tap ac output load equivalent ......................... 19 tap dc electrical characteristics and operating conditions ..................................................... 19 identification register definitions ................................ 20 scan register sizes ....................................................... 20 identification codes ....................................................... 20 boundary scan order .................................................... 21 boundary scan order .................................................... 22 maximum ratings ........................................................... 23 operating range ............................................................. 23 electrical characteristics ............................................... 23 capacitance .................................................................... 24 thermal resistance ........................................................ 24 ac test loads and waveforms ..................................... 25 switching characteristics .............................................. 26 switching waveforms .................................................... 27 ordering information ...................................................... 30 ordering code definitions ..... .................................... 30 package diagrams .......................................................... 31 acronyms ........................................................................ 34 document conventions ................................................. 34 units of measure ....................................................... 34 document history page ................................................. 35 sales, solutions, and legal information ...................... 37 worldwide sales and design s upport ......... .............. 37 products .................................................................... 37 psoc solutions ......................................................... 37
cy7c1371d cy7c1373d document number: 38-05556 rev. *l page 5 of 37 pin configurations figure 1. 100-pin tqfp (14 20 1.4 mm) pinout cy7c1371d a a a a a1 a0 nc/288m nc/144m v ss v dd nc/36m a a a a a a dqp b dq b dq b v ddq v ss dq b dq b dq b dq b v ss v ddq dq b dq b v ss nc v dd dq a dq a v ddq v ss dq a dq a dq a dq a v ss v ddq dq a dq a dqp a dqp c dq c dq c v ddq v ss dq c dq c dq c dq c v ss v ddq dq c dq c nc v dd nc v ss dq d dq d v ddq v ss dq d dq d dq d dq d v ss v ddq dq d dq d dqp d a a ce 1 ce 2 bw d bw c bw b bw a ce 3 v dd v ss clk we cen oe a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 a a adv/ld zz mode nc/72m byte a byte b byte d byte c a
cy7c1371d cy7c1373d document number: 38-05556 rev. *l page 6 of 37 figure 2. 100-pin tqfp (14 20 1.4 mm) pinout cy7c1373d pin configurations (continued) a a a a a1 a0 nc/288m nc/144m v ss v dd nc/36m a a a a a a a nc nc v ddq v ss nc dqp a dq a dq a v ss v ddq dq a dq a v ss nc v dd dq a dq a v ddq v ss dq a dq a nc nc v ss v ddq nc nc nc nc nc nc v ddq v ss nc nc dq b dq b v ss v ddq dq b dq b nc v dd nc v ss dq b dq b v ddq v ss dq b dq b dqp b nc v ss v ddq nc nc nc a a ce 1 ce 2 nc nc bw b bw a ce 3 v dd v ss clk we cen oe a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 a a adv/ld zz mode nc/72m byte a byte b a
cy7c1371d cy7c1373d document number: 38-05556 rev. *l page 7 of 37 figure 3. 119-ball bga (14 22 2.4 mm) pinout pin configurations (continued) 234567 1 a b c d e f g h j k l m n p r t u v ddq nc/576m nc/1g dqp c dq c dq d dq c dq d aa aav ddq ce 2 a dq c v ddq dq c v ddq v ddq v ddq dq d dq d nc/144m nc v ddq v dd clk v dd v ss v ss v ss v ss v ss v ss v ss v ss nc nc nc nc tdo tck tdi tms nc/36m nc/72m nc/288m v ddq v ddq v ddq aaa a ce 3 a a a a a a a0 a1 dq a dq c dq a dq a dq a dq b dq b dq b dq b dq b dq b dq b dq a dq a dq a dq a dq b v dd dq c dq c dq c v dd dq d dq d dq d dq d adv/ld nc ce 1 oe a we v ss v ss v ss v ss v ss v ss v ss v ss dqp a mode dqp d dqp b bw b bw c nc v dd nc bw a nc cen bw d zz a cy7c1371d (512 k 36)
cy7c1371d cy7c1373d document number: 38-05556 rev. *l page 8 of 37 figure 4. 165-ball fbga (13 15 1.4 mm) pinout pin configurations (continued) cy7c1373d (1 m 18) 234 567 1 a b c d e f g h j k l m n p r tdo nc/576m nc/1g nc nc dqp b nc dq b ce 1 nc ce 3 bw b cen a ce2 nc dq b dq b mode nc dq b dq b nc nc nc nc/36m nc/72m v ddq nc bw a clk we v ss v ss v ss v ss v ddq v ss v dd v ss v ss v ss v ss v ss v ss v ddq v ddq nc v ddq v ddq v ddq v ddq a a v dd v ss v dd v ss v ss v ddq v dd v ss v dd v ss v dd v ss v ss v ss v dd v dd v ss v dd v ss v ss nc tck v ss tdi a a dq b v ss nc v ss dq b nc nc v ss v ss v ss v ss nc v ss a1 dq b nc nc/144m nc v ddq v ss tms 891011 nc/288m a a adv/ld a oe a nc v ss v ddq nc dqp a v ddq v dd nc dq a dq a nc nc nc dq a nc v dd v ddq v dd v ddq dq a v dd nc v dd nc v dd v ddq dq a v ddq v dd v dd v ddq v dd v ddq nc v ddq a a v ss a a a dq a nc nc zz dq a nc nc dq a a v ddq a a0 a v ss nc a
cy7c1371d cy7c1373d document number: 38-05556 rev. *l page 9 of 37 pin definitions name i/o description a 0 , a 1 , a input- synchronous address inputs used to select one of the address locations . sampled at the rising edge of the clk. a [1:0] are fed to the tw o-bit burst counter. bw a , bw b , bw c , bw d input- synchronous byte write inputs, active low . qualified with we to conduct writes to the sram. sampled on the rising edge of clk. we input- synchronous write enable input, active low . sampled on the rising edge of clk if cen is active low. this signal must be asserted low to initiate a write sequence. adv/ld input- synchronous advance/load input . used to advance the on-chip address co unter or load a new address. when high (and cen is asserted low) the inter nal burst counter is advanced. when low, a new address can be loaded into the device for an access. after being deselected, adv/ld must be driven low to load a new address. clk input-clock clock input . used to capture all synchronous inputs to the device. clk is qualified with cen . clk is only recognized if cen is active low. ce 1 input- synchronous chip enable 1 input, active low . sampled on the rising edge of clk. used in conjunction with ce 2 and ce 3 to select/deselect the device. ce 2 input- synchronous chip enable 2 input, active high . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 3 to select/deselect the device. ce 3 input- synchronous chip enable 3 input, active low . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 2 to select/deselect the device. oe input- asynchronous output enable, asynchronous input, active low . combined with the synchronous logic block inside the device to control the directio n of the i/o pins. when low, the i/o pins are allowed to behave as outputs. when deasserted high, i/o pins are tristated, and act as input data pins. oe is masked during the data portion of a write sequenc e, during the first clock when emergi ng from a deselected state, when the device has been deselected. cen input- synchronous clock enable input, active low . when asserted low the clock signal is recognized by the sram. when deasserted high the clock signal is masked. while deasserting cen does not deselect the device, use cen to extend the previous cycle when required. zz input- asynchronous zz ?sleep? input . this active high input plac es the device in a non-time critical ?sleep? condition with data integrity preserved. for normal operation, this pin has to be low or left floating. zz pin has an internal pull-down. dq s i/o- synchronous bidirectional data i/o lines . as inputs, they feed into an on-chip da ta register that is triggered by the rising edge of clk. as outputs, t hey deliver the data contained in t he memory location specified by the addresses presented during the previous clock rise of the read cycle. the direction of the pins is controlled by oe . when oe is asserted low, the pins b ehave as outputs. when high, dq s and dqp [a:d] are placed in a tristate condi tion.the outputs are autom atically tristated during the data portion of a write sequence, during the fi rst clock when emerging from a des elected state, and when the device is deselected, regardless of the state of oe . dqp x i/o- synchronous bidirectional data parity i/o lines. functionally, these signals are identical to dq s . mode input strap pin mode input. selects the bu rst order of the device. when tied to gnd selects linear burst sequence. when tied to v dd or left floating selects interleaved burst sequence. v dd power supply power supply inputs to the core of the device . v ddq i/o power supply power supply for the i/o circuitry . v ss ground ground for the device .
cy7c1371d cy7c1373d document number: 38-05556 rev. *l page 10 of 37 functional overview the cy7c1371d/cy7c1373d is a synchronous flow through burst sram designed specifically to eliminate wait states during write-read transitions. all synchronous inputs pass through input registers controlled by the rising edge of the clock. the clock signal is qualified with the clock enable input signal (cen ). if cen is high, the clock signal is not recognized and all internal states are maintained. all synch ronous operations are qualified with cen . maximum access delay from the clock rise (t cdv ) is 6.5 ns (133-mhz device). accesses can be initiated by asserting all three chip enables (ce 1 , ce 2 , ce 3 ) active at the rising edge of the clock. if clock enable (cen ) is active low and adv/ld is asserted low, the address presented to the device is latched. the access can either be a read or write oper ation, depending on the status of the write enable (we ). bw x can be used to conduct byte write operations. write operations are qualified by the write enable (we ). all writes are simplified with on- chip synchronous self-t imed write circuitry. three synchronous chip enables (ce 1 , ce 2 , ce 3 ) and an asynchronous output enable (oe ) simplify depth expansion. all operations (reads, writes, and de selects) are pipelined. adv/ld must be driven low after the device has been deselected to load a new address for the next operation. single read accesses a read access is initiated when these conditions are satisfied at clock rise: cen is asserted low ce 1 , ce 2 , and ce 3 are all asserted active the write enable input signal we is deasserted high adv/ld is asserted low. the address presented to the address inputs is latched into the address register and presented to the memory array and control logic. the control logic determines that a read access is in progress and allows the requested data to propagate to the output buffers. the data is av ailable within 6.5 ns (133-mhz device) provided oe is active low. after the first clock of the read access, the output buffers are controlled by oe and the internal control logic. oe must be driven low in order for the device to drive out the requested data. on the subsequent clock, another operation (read/ write/deselect) can be initiated. when the sram is deselected at clock rise by one of the chip enable signals, its output is tristated immediately. burst read accesses the cy7c1371d/cy7c1373d has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four reads without reasserting the address inputs. adv/ld must be driven low to load a new address into the sram, as described in the single read accesses section above. the sequence of the burst counter is determined by the mode input signal. a low input on mode selects a linear burst mode, a high selects an interleaved burst sequence. both burst counters use a 0 and a 1 in the burst sequence, and wraps around when incremented sufficiently. a high input on adv/ld increments the internal burst count er regardless of the state of chip enable inputs or we . we is latched at the beginning of a burst cycle. therefore, the type of access (read or write) is maintained throughout the burst sequence. single write accesses write access are initiated when the following conditions are satisfied at clock rise: (1) cen is asserted low, (2) ce 1 , ce 2 , and ce 3 are all asserted active, and (3) the write signal we is asserted low. the address pr esented to the address bus is loaded into the address register. the write signals are latched into the control logic block. the data lines are automatically tristated regardless of the state of the oe input signal. this allows the external logic to present the data on dqs and dqp x . on the next clock rise the data presented to dqs and dqp x (or a subset for byte write operations, see truth table for details) inputs is latched into the device and the write is complete. additional accesses (read/write/deselect) can be initiated on this cycle. the data written during the writ e operation is controlled by bw x signals. the cy7c1371d/cy7c1373d provides byte write capability that is described in t he truth table. asserting the write tdo jtag serial output synchronous serial data-out to the jtag circuit . delivers data on the negative edge of tck. if the jtag feature is not being used, this pin must be left unconnect ed. this pin is not available on tqfp packages. tdi jtag serial input synchronous serial data-in to the jtag circuit . sampled on the rising edge of tck. if the jtag feature is not being used, this pin can be left floating or connected to v dd through a pull up resistor. this pin is not available on tqfp packages. tms jtag serial input synchronous serial data-in to the jtag circuit . sampled on the rising edge of tck. if the jtag feature is not being used, this pin can be disconnected or connected to v dd . this pin is not available on tqfp packages. tck jtag- clock clock input to the jtag circuitry . if the jtag feature is not being used, this pin must be connected to v ss . this pin is not available on tqfp packages. nc ? no connects . not internally connected to the die. nc/(36 m, 72 m, 144 m, 288m, 576m, 1g)are address expansion pins and are not internally connected to the die. pin definitions (continued) name i/o description
cy7c1371d cy7c1373d document number: 38-05556 rev. *l page 11 of 37 enable input (we ) with the selected by te write select input selectively writes to only the de sired bytes. bytes not selected during a byte write operation remains unaltered. a synchronous self-timed write mechanism has been provided to simplify the write operations. byte write capability has been included to greatly simplify read/modify/write sequences, which can be reduced to simple byte write operations. because the cy7c1371d/cy7c1373d is a common i/o device, data must not be driven into the device while the outputs are active. the output enable (oe ) can be deasserted high before presenting data to the dqs and dqp x inputs. doing so tristates the output drivers. as a sa fety precaution, dqs and dqp x are automatically tristated during the data portion of a write cycle, regardless of the state of oe . burst write accesses the cy7c1371d/cy7c1373d has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four write operations without reasserting the address inputs. adv/ld must be driven low to load the initial address, as described in the single write accesses section above. when adv/ld is driven high on the subsequent clock rise, the chip enables (ce 1 , ce 2 , and ce 3 ) and we inputs are ignored and the burst counter is incremented. the correct bw x inputs must be driven in each cycle of the burst write, to write the correct bytes of data. sleep mode the zz input pin is an asynchronous input. asserting zz places the sram in a power conservation ?sleep? mode. two clock cycles are required to enter into or exit from this ?sleep? mode. while in this mode, data integrity is guaranteed. accesses pending when entering the ?sleep? mode are not considered valid nor is the completion of the operation guaranteed. the device must be deselected prior to entering the ?sleep? mode. ce 1 , ce 2 , and ce 3 , must remain inactive for the duration of t zzrec after the zz input returns low. interleaved burst address table (mode = floating or v dd ) first address a1:a0 second address a1:a0 third address a1:a0 fourth address a1:a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst address table (mode = gnd) first address a1:a0 second address a1:a0 third address a1:a0 fourth address a1:a0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 zz mode electrical characteristics parameter description test conditions min max unit i ddzz sleep mode standby current zz > v dd ? ? 0.2 v ? 80 ma t zzs device operation to zz zz > v dd ? 0.2 v ? 2t cyc ns t zzrec zz recovery time zz < 0.2 v 2t cyc ?ns t zzi zz active to sleep current th is parameter is sampled ? 2t cyc ns t rzzi zz inactive to exit sleep curr ent this parameter is sampled 0 ? ns
cy7c1371d cy7c1373d document number: 38-05556 rev. *l page 12 of 37 truth table the truth table for cy7c1371d, and cy7c1373d are as follows. [1, 2, 3, 4, 5, 6, 7] operation address used ce 1 ce 2 ce 3 zz adv/ld we bw x oe cen clk dq deselect cycle none h x x l l x x x l l->h tristate deselect cycle none x x h l l x x x l l->h tristate deselect cycle none x l x l l x x x l l->h tristate continue deselect cycle none x x x l h x x x l l->h tristate read cycle (begin burst) exter nal l h l l l h x l l l->h data out (q) read cycle (continue burst) nex t x x x l h x x l l l->h data out (q) nop/dummy read (begin burst) external l h l l l h x h l l->h tristate dummy read (continue burst) next x x x l h x x h l l->h tristate write cycle (begin burst) external l h l l l l l x l l->h data in (d) write cycle (continue burst) next x x x l h x l x l l->h data in (d) nop/write abort (begin burst) none l h l l l l h x l l->h tristate write abort (continue burst) n ext x x x l h x h x l l->h tristate ignore clock edge (stall) current x x x l x x x x h l->h ? sleep mode none x x xh x xxxx x tristate partial truth table for read/write the partial truth table for read/write for cy7c1371d follows. [1, 2, 8] function (cy7c1371d) we bw a bw b bw c bw d read h x x x x write no bytes written l h h h h write byte a ? (dq a and dqp a ) l lhhh write byte b ? (dq b and dqp b )lhlhh write byte c ? (dq c and dqp c )lhhlh write byte d ? (dq d and dqp d )lhhhl write all bytes l l l l l notes 1. x = ?don't care.? h = logic high, l = logic low. bw x = 0 signifies at least one byte write select is active, bw x = valid signifies that the desired byte write selects are asserted, see truth table for details. 2. write is defined by bw x , and we . see truth table for read/write. 3. when a write cycle is detected, all i/os are tristated, even during byte writes. 4. the dqs and dqp x pins are controlled by the current cycle and the oe signal. oe is asynchronous and is not sampled with the clock. 5. cen = h, inserts wait states. 6. device powers up deselected and the i/os in a tristate condition, regardless of oe . 7. oe is asynchronous and is not sampled with the clock rise. it is masked internally during write cycles. during a read cycle dqs a nd dqp x = tristate when oe is inactive or when the device is deselected, and dqs and dqp x = data when oe is active. 8. table only lists a partial listing of the by te write combinations. any combination of bw x is valid appropriate write is bas ed on which byte write is active.
cy7c1371d cy7c1373d document number: 38-05556 rev. *l page 13 of 37 partial truth table for read/write the partial truth table for read/write for cy7c1373d follows. [9, 10, 11] function (cy7c1373d) we bw a bw b read h x x write - no bytes written l h h write byte a ? (dq a and dqp a )llh write byte b ? (dq b and dqp b )lhl write all bytes l l l notes 9. x = ?don't care.? h = logic high, l = logic low. bw x = 0 signifies at least one byte write select is active, bw x = valid signifies that the desired byte write selects are asserted, see truth table for details. 10. write is defined by bw x , and we . see truth table for read/write. 11. table only lists a partial listing of the by te write combinations. any combination of bw x is valid appropriate write is bas ed on which byte write is active.
cy7c1371d cy7c1373d document number: 38-05556 rev. *l page 14 of 37 ieee 1149.1 serial boundary scan (jtag) the cy7c1371d/cy7c1373d incorporates a serial boundary scan test access port (tap).thi s part is fully compliant with 1149.1. the tap operates using jedec-standard 3.3 v or 2.5 v i/o logic levels. the cy7c1371d/cy7c1373d contains a tap controller, instruction register, boundary scan register, bypass register, and id register. disabling the jtag feature it is possible to operate the sram without using the jtag feature. to disable the tap co ntroller, tck must be tied low (v ss ) to prevent clocking of the device. tdi and tms are internally pulled up and may be unconnected. they may alternately be connected to v dd through a pull up resistor. tdo must be left unconnected. upon power-up, the device is up in a reset state which does not interfere with the operation of the device. test access port (tap) test clock (tck) the test clock is used only with the tap controller. all inputs are captured on the rising edge of tc k. all outputs are driven from the falling edge of tck. test mode select (tms) the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. it is allowable to leave this ball unconnected if the tap is not used. the ball is pulled up internally, resulting in a logic high level. test data-in (tdi) the tdi ball is used to serially input information into the registers and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. for information on loading the instruction register, see tap controller state diagram on page 16 . tdi is internally pulled up and can be unconnected if the tap is unus ed in an application. tdi is connected to the most signific ant bit (msb) of any register. test data-out (tdo) the tdo output ball is used to serially clock data-out from the registers. the output is active depending upon the current state of the tap state machine (see identification codes on page 20 ). the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any register. performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. this reset does no t affect the operation of the sram and may be performed while the sram is operating. at power-up, the tap is reset internally to ensure that tdo comes up in a high z state. tap registers registers are connected betwe en the tdi and tdo balls and allow data to be scanned into and out of the sram test circuitry. only one register can be selected at a time through the instruction register. data is serially loaded into the tdi ball on the rising edge of tck. data is output on the tdo ball on the falling edge of tck. instruction register three-bit instructions can be serially loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo balls as shown in the tap controller block diagram on page 17 . upon power-up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state as described in the previous section. when the tap controller is in th e capture-ir state, the two least significant bits are loaded with a binary ?01? pattern to allow for fault isolation of the board level serial test data path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. the bypass register is a single-bit register that can be placed between the tdi and tdo balls. this allows data to be shifted through the sram with minimal delay. the by pass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all the input and bidirectional balls on the sram. the boundary scan register is loaded with the contents of the ram i/o ring when the tap controll er is in the capture-dr state and is then placed between the tdi and tdo balls when the controller is moved to the shift-dr state. the extest, sample/preload and sample z instructions can be used to capture the contents of the i/o ring. the boundary scan order on page 21 and boundary scan order on page 22 show the order in which the bits are connected. each bit corresponds to one of the bu mps on the sram package. the msb of the register is con nected to tdi and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific, 32-bit code during the capture-dr state when the idcode command is loaded in the instruction register . the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. the id regist er has a vendor code and other information described in the identification register definitions on page 20 . tap instruction set overview eight different instructions are possible with the three bit instruction register. all combinations are listed in the identifi- cation codes on page 20 . three of these instructions are listed as reserved and must not be us ed. the other five instructions are described in detail below. instructions are loaded into the tap controller during the shift-ir state when the instruction register is placed between tdi and tdo. during this state, instructions are shifted through the instruction register through the tdi and tdo balls. to execute
cy7c1371d cy7c1373d document number: 38-05556 rev. *l page 15 of 37 the instruction after it is shifted in, the tap controller needs to be moved into the update-ir state. extest the extest instruction enables the preloaded data to be driven out through the system output pins . this instruction also selects the boundary scan register to be connected for serial access between the tdi and tdo in the shift-dr controller state. idcode the idcode instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. it also places the instruction register between the tdi and tdo balls and allows the idcode to be shifted out of the device when the tap controller enters the shift-dr state. the idcode instruction is loade d into the instruction register upon power-up or whenever the tap controller is supplied a test logic reset state. sample z the sample z instruction causes the boundary scan register to be connected between the tdi and tdo balls when the tap controller is in a shift-dr state. it also places all sram outputs into a high z state. sample/preload sample/preload is a 1149.1 mandatory instruction. when the sample/preload instructions are loaded into the instruction register and the tap controller is in the capture-dr state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. the user must be aware that t he tap controller clock can only operate at a frequency up to 20 mhz, while the sram clock operates more than an order of magnitude faster. because there is a large difference in the clock frequencies, it is possible that during the capture-dr state, an input or output undergoes a transition. the tap may then try to capture a signal while in transition (metastable state). this does not harm the device, but there is no guarantee as to the value that is captured. repeatable results may not be possible. to guarantee that the boundary scan register captures the correct value of a signal, the sram signal must be stabilized long enough to meet the tap cont roller?s capture setup plus hold times (t cs and t ch ). the sram clock input might not be captured correctly if there is no way in a de sign to stop (or slow) the clock during a sample/preload instruction. if this is an issue, it is still possible to capture all othe r signals and simply ignore the value of the ck and ck captured in the boundary scan register. after the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the boundary scan register between the tdi and tdo pins. preload allows an initial data pattern to be placed at the latched parallel outputs of the boun dary scan register cells prior to the selection of another boundary scan test operation. the shifting of data for the sample and preload phases can occur concurrently when required ? that is, while data captured is shifted out, the preloaded data can be shifted in. bypass when the bypass instruction is loaded in the instruction register and the tap is placed in a shift- dr state, the bypass register is placed between the tdi and tdo balls. the advantage of the bypass instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. extest output bus tristate ieee standard 1149.1 mandates that the tap controller be able to put the output bus into a tristate mode. the boundary scan register has a special bit located at bit #85 (for 119-ball bga package) or bit #89 (for 165-ball fbga package). when this scan cell , called the ?extest output bus tristate,? is latched into the preload register during the ?update-dr? state in the tap controller, it directly controls the state of the output (q-bus) pins, when the extest is entered as the current instruction. when high , it enables the output buffers to drive the output bus. when low, this bit places the output bus into a high z condition. this bit can be set by entering the sample/preload or extest command, and then shifting the desired bit into that cell, during the ?shift-dr? state. during ?update-dr,? the value loaded into that shift-register cell latches into the preload register. when the extest instruction is entered, this bit directly controls the output q-bus pins. note that this bit is preset high to enable the output when the device is powered-up, and also when the tap controller is in the ?test-logic-reset? state. reserved these instructions are not im plemented but are reserved for future use. do not use these instructions.
cy7c1371d cy7c1373d document number: 38-05556 rev. *l page 16 of 37 the 0/1 next to each state represents t he value of tms at the rising edge of tck. tap controller state diagram test-logic reset run-test/ idle select dr-scan select ir-scan capture-dr shift-dr capture-ir shift-ir exit1-dr pause-dr exit1-ir pause-ir exit2-dr update-dr exit2-ir update-ir 1 1 1 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0
cy7c1371d cy7c1373d document number: 38-05556 rev. *l page 17 of 37 tap controller block diagram bypass register 0 instruction register 0 1 2 identication register 0 1 2 29 30 31 . . . boundary scan register 0 1 2 . . x . . . selection circuitry tck tms tap controller tdi td o selection circuitry tap tiing figure 5. tap tiing t tl test clock (tck) 123456 t est mode select (tms) t th test data-out (tdo) t cyc test data-in (tdi) t tmsh t tmss t tdih t tdis t tdox t tdov dont care undefined
cy7c1371d cy7c1373d document number: 38-05556 rev. *l page 18 of 37 tap ac switchi ng characteristics over the operating range parameter [12, 13] description min max unit clock t tcyc tck clock cycle time 50 ? ns t tf tck clock frequency ? 20 mhz t th tck clock high time 20 ? ns t tl tck clock low time 20 ? ns output times t tdov tck clock low to tdo valid ? 10 ns t tdox tck clock low to tdo invalid 0 ? ns setup times t tmss tms setup to tck clock rise 5 ? ns t tdis tdi setup to tck clock rise 5 ? ns t cs capture setup to tck rise 5 ? ns hold times t tmsh tms hold after tck clock rise 5 ? ns t tdih tdi hold after clock rise 5 ? ns t ch capture hold after clock rise 5 ? ns notes 12. t cs and t ch refer to the setup and hold time requirements of latching data from the boundary scan register. 13. test conditions are specified using the load in tap ac test conditions. t r /t f = 1 ns.
cy7c1371d cy7c1373d document number: 38-05556 rev. *l page 19 of 37 3.3 v tap ac test conditions input pulse levels ...............................................v ss to 3.3 v input rise and fall times ...................................................1 ns input timing reference levels .. ....................................... 1.5 v output reference levels ................................................ 1.5 v test load termination supply voltage ............................ 1.5 v 2.5 v tap ac test conditions input pulse level ................................................. v ss to 2.5 v input rise and fall time ....................................................1 ns input timing reference levels ... ................................... .1.25 v output reference levels .............................................. 1.25 v test load termination supply vo ltage .......................... 1.25 v 3.3 v tap ac out put load equivalent tdo 1.5v 20pf z = 50 o 50 tdo 1.25v 20pf z = 50 o 50 (0 c < t a < +70 c; v dd = 3.3 v 0.165 v unless otherwise noted) parameter [14] description description conditions min max unit v oh1 output high voltage i oh = ?4.0 ma v ddq = 3.3 v 2.4 ? v i oh = ?1.0 ma v ddq = 2.5 v 2.0 ? v v oh2 output high voltage i oh = ?100 a v ddq = 3.3 v 2.9 ? v v ddq = 2.5 v 2.1 ? v v ol1 output low voltage i ol = 8.0 ma v ddq = 3.3 v ? 0.4 v i ol = 1.0 ma v ddq = 2.5 v ? 0.4 v v ol2 output low voltage i ol = 100 a v ddq = 3.3 v ? 0.2 v v ddq = 2.5 v ? 0.2 v v ih input high voltage v ddq = 3.3 v 2.0 v dd + 0.3 v v ddq = 2.5 v 1.7 v dd + 0.3 v v il input low voltage v ddq = 3.3 v ?0.5 0.7 v v ddq = 2.5 v ?0.3 0.7 v i x input load current gnd < v in < v ddq ?5 5 a note 14. all voltages referenced to v ss (gnd).
cy7c1371d cy7c1373d document number: 38-05556 rev. *l page 20 of 37 identification regi ster definitions instruction field cy7c1371d (512 k 36) cy7c1373d (1 m 18) description revision number (31:29) 000 000 describes the version number device depth (28:24) 01011 01011 reserved for internal use device width (23:18) 001001 001001 defines memory type and architecture cypress device id (17:12) 100101 0 10101 defines width and density cypress jedec id code (11:1) 00000110100 00000110100 allows unique identification of sram vendor id register presence indicator (0) 1 1 indicates the presence of an id register scan register sizes register name bit size ( 36) bit size ( 18) instruction 3 3 bypass 11 id 32 32 boundary scan order (119-ball bga package) 85 ? boundary scan order (165-ball fbga package) ? 89 identification codes instruction code description extest 000 captures i/o ring contents. places the boundary scan register between tdi and tdo. forces all sram outputs to high z state. idcode 001 loads the id register with the vendor id code and places the register between tdi and tdo. this operation does not affect sram operations. sample z 010 captures i/o ring contents. places th e boundary scan register between tdi and tdo. forces all sram output drivers to a high z state. reserved 011 do not use: this instruct ion is reserved for future use. sample/preload 100 captures i/o ring contents. places the boundary scan register between tdi and tdo. does not affect sram operation. reserved 101 do not use: this instruct ion is reserved for future use. reserved 110 do not use: this instruct ion is reserved for future use. bypass 111 places the bypass register between tdi and tdo. this operation does not affect sram operations.
cy7c1371d cy7c1373d document number: 38-05556 rev. *l page 21 of 37 boundary scan order 119-ball bga [15, 16] bit # ball id bit # ball id bit # ball id bit # ball id 1 h4 23 f6 45 g4 67 l1 2t4 24e7 46a4 68m2 3 t5 25d7 47g3 69n1 4t6 26h7 48c3 70p1 5r5 27g6 49b2 71k1 6l5 28e6 50b3 72l2 7r6 29d6 51a3 73 n2 8u6 30c7 52c2 74p2 9r7 31b7 53a2 75r3 10 t7 32 c6 54 b1 76 t1 11 p6 33 a6 55 c1 77 r1 12 n7 34 c5 56 d2 78 t2 13 m6 35 b5 57 e1 79 l3 14 l7 36 g5 58 f2 80 r2 15 k6 37 b6 59 g1 81 t3 16 p7 38 d4 60 h2 82 l4 17 n6 39 b4 61 d1 83 n4 18 l6 40 f4 62 e2 84 p4 19 k7 41 m4 63 g2 85 internal 20 j5 42 a5 64 h1 21 h6 43 k4 65 j3 22 g7 44 e4 66 2k notes 15. balls which are nc (no connect) are pre-set low. 16. bit# 85 is pre-set high.
cy7c1371d cy7c1373d document number: 38-05556 rev. *l page 22 of 37 boundary scan order 165-ball bga [17, 18] bit # ball id bit # ball id bit # ball id 1 n6 31 d10 61 g1 2n7 32c11 62d2 3n10 33a11 63e2 4p11 34b11 64f2 5p8 35a10 65g2 6r8 36b10 66h1 7r9 37a9 67h3 8p9 38b9 68j1 9p10 39c10 69k1 10 r10 40 a8 70 l1 11 r11 41 b8 71 m1 12 h11 42 a7 72 j2 13 n11 43 b7 73 k2 14 m11 44 b6 74 l2 15 l11 45 a6 75 m2 16 k11 46 b5 76 n1 17 j11 47 a5 77 n2 18 m10 48 a4 78 p1 19 l10 49 b4 79 r1 20 k10 50 b3 80 r2 21 j10 51 a3 81 p3 22 h9 52 a2 82 r3 23 h10 53 b2 83 p2 24 g11 54 c2 84 r4 25 f11 55 b1 85 p4 26 e11 56 a1 86 n5 27 d11 57 c1 87 p6 28 g10 58 d1 88 r6 29 f10 59 e1 89 internal 30 e10 60 f1 note 17. balls which are nc (no connect) are pre-set low. 18. bit# 89 is pre-set high.
cy7c1371d cy7c1373d document number: 38-05556 rev. *l page 23 of 37 maximum ratings exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature .. ............... ............... ?65 c to +150 c ambient temperature with power applied ............ ............... ............... ?55 c to +125 c supply voltage on v dd relative to gnd .......?0.5 v to +4.6 v supply voltage on v ddq relative to gnd ...... ?0.5 v to +v dd dc voltage applied to outputs in tristate ...........................................?0.5 v to v ddq + 0.5 v dc input voltage ................................. ?0.5 v to v dd + 0.5 v current into outputs (low) ........................................ 20 ma static discharge voltage (mil-std-883, method 3015) ................................. > 2001 v latch up current ..................................................... > 200 ma operating range range ambient temperature v dd v ddq commercial 0 c to +70 c 3.3 v ? ? 5% / + 10% 2.5 v ? 5% to v dd industrial ?40 c to +85 c electrical characteristics over the operating range parameter [19, 20] description test conditions min max unit v dd power supply voltage 3.135 3.6 v v ddq i/o supply voltage for 3.3 v i/o 3.135 v dd v for 2.5 v i/o 2.375 2.625 v v oh output high voltage for 3.3 v i/o, i oh = ?4.0 ma 2.4 ? v for 2.5 v i/o, i oh = ?1.0 ma 2.0 ? v v ol output low voltage for 3.3 v i/o, i ol = 8.0 ma ? 0.4 v for 2.5 v i/o, i ol = 1.0 ma ? 0.4 v v ih input high voltage [19] for 3.3 v i/o 2.0 v dd + 0.3 v for 2.5 v i/o 1.7 v dd + 0.3 v v il input low voltage [19] for 3.3 v i/o ?0.3 0.8 v for 2.5 v i/o ?0.3 0.7 v i x input leakage current except zz and mode gnd ? v i ? v ddq ?5 5 ? a input current of mode input = v ss ?30 ? ? a input = v dd ? 5 ? a input current of zz input = v ss ?5 ? ? a input = v dd ? 30 ? a i dd v dd operating supply current v dd = max, i out = 0 ma, f = f max = 1/t cyc 7.5 ns cycle, 133 mhz ?210ma 10 ns cycle, 100 mhz ? 175 ma i sb1 automatic ce power-down current ? ttl inputs v dd = max, device deselected, v in ? v ih or v in ? v il , f = f max , inputs switching 7.5 ns cycle, 133 mhz ?140ma 10 ns cycle, 100 mhz ? 120 ma i sb2 automatic ce power-down current ? cmos inputs v dd = max, device deselected, v in ? 0.3 v or v in > v dd ? 0.3 v, f = 0, inputs static all speeds ? 70 ma notes 19. overshoot: v ih(ac) < v dd + 1.5 v (pulse width less than t cyc /2), undershoot: v il(ac) > ?2 v (pulse width less than t cyc /2). 20. t power-up : assumes a linear ramp from 0 v to v dd(min) within 200 ms. during this time v ih < v dd and v ddq < v dd .
cy7c1371d cy7c1373d document number: 38-05556 rev. *l page 24 of 37 i sb3 automatic ce power-down current ? cmos inputs v dd = max, device deselected, v in ? 0.3 v or v in > v ddq ? 0.3 v, f = f max , inputs switching 7.5 ns cycle, 133 mhz ?130ma 10 ns cycle, 100 mhz ? 110 ma i sb4 automatic ce power-down current ? ttl inputs v dd = max, device deselected, v in ? v dd ? 0.3 v or v in ? 0.3 v, f = 0, inputs static all speeds ? 80 ma capacitance parameter [21] description test conditions 100-pin tqfp package 119-ball bga package 165-ball fbga package unit c in input capacitance t a = 25 ? c, f = 1 mhz, v dd = 3.3 v, v ddq = 2.5 v 589pf c clk clock input capacitance 5 8 9 pf c io input/output capacitance 5 8 9 pf thermal resistance parameter [21] description test conditions 100-pin tqfp package 119-ball bga package 165-ball fbga package unit ? ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, according to eia/jesd51. 28.66 23.8 20.7 ? c/w ? jc thermal resistance (junction to case) 4.08 6.2 4.0 ? c/w electrical characteristics (continued) over the operating range parameter [19, 20] description test conditions min max unit note 21. tested initially and after any design or proc ess change that may affect these parameters.
cy7c1371d cy7c1373d document number: 38-05556 rev. *l page 25 of 37 ac test loads and waveforms figure 6. ac test loads and waveforms output r = 317 ? r = 351 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v t = 1.5 v 3.3 v all input pulses v ddq gnd 90% 10% 90% 10% ? 1ns ? 1ns (c) output r = 1667 ? r = 1538 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v t = 1.25 v 2.5 v all input pulses v ddq gnd 90% 10% 90% 10% ? 1ns ? 1ns (c) 3.3 v i/o test load 2.5 v i/o test load
cy7c1371d cy7c1373d document number: 38-05556 rev. *l page 26 of 37 switching characteristics over the operating range parameter [22, 23] description 133 mhz 100 mhz unit min max min max t power v dd (typical) to the first access [24] 1?1?ms clock t cyc clock cycle time 7.5 ? 10 ? ns t ch clock high 2.1 ? 2.5 ? ns t cl clock low 2.1 ? 2.5 ? ns output times t cdv data output valid after clk rise ? 6.5 ? 8.5 ns t doh data output hold after clk rise 2.0 ? 2.0 ? ns t clz clock to low z [25, 26, 27] 2.0?2.0?ns t chz clock to high z [25, 26, 27] ? 4.0 ? 5.0 ns t oev oe low to output valid ? 3.2 ? 3.8 ns t oelz oe low to output low z [25, 26, 27] 0?0?ns t oehz oe high to output high z [25, 26, 27] ? 4.0 ? 5.0 ns setup times t as address setup before clk rise 1.5 ? 1.5 ? ns t als adv/ld setup before clk rise 1.5 ? 1.5 ? ns t wes we , bw x setup before clk rise 1.5 ? 1.5 ? ns t cens cen setup before clk rise 1.5 ? 1.5 ? ns t ds data input setup before clk rise 1.5 ? 1.5 ? ns t ces chip enable setup before clk rise 1.5 ? 1.5 ? ns hold times t ah address hold after clk rise 0.5 ? 0.5 ? ns t alh adv/ld hold after clk rise 0.5 ? 0.5 ? ns t weh we , bw x hold after clk rise 0.5 ? 0.5 ? ns t cenh cen hold after clk rise 0.5 ? 0.5 ? ns t dh data input hold after clk rise 0.5 ? 0.5 ? ns t ceh chip enable hold after clk rise 0.5 ? 0.5 ? ns notes 22. timing reference level is 1.5 v when v ddq = 3.3 v and is 1.25 v when v ddq = 2.5 v. 23. test conditions shown in (a) of figure 6 on page 25 unless otherwise noted. 24. this part has a voltage regulator internally; t power is the time that the power needs to be supplied above v dd(minimum) initially, before a read or write operation can be initiated. 25. t chz , t clz , t oelz , and t oehz are specified with ac test conditions shown in part (b) of figure 6 on page 25 . transition is measured 200 mv from steady-state voltage. 26. at any voltage and temperature, t oehz is less than t oelz and t chz is less than t clz to eliminate bus contention between srams when sharing the same data bus. these specifications do not impl y a bus contention condition, but reflect paramete rs guaranteed over worst case user conditions . device is designed to achieve high z prior to low z under the same system conditions. 27. this parameter is sampled and not 100% tested.
cy7c1371d cy7c1373d document number: 38-05556 rev. *l page 27 of 37 switching waveforms figure 7. read/write waveforms [28, 29, 30] write d(a1) 123 456789 clk t cyc t cl t ch 10 ce t ceh t ces we cen t cenh t cens bw x adv/ld t ah t as address a1 a2 a3 a4 a5 a6 a7 t dh t ds dq c ommand t clz d(a1) d(a2) q(a4) q(a3) d(a2+1) t doh t chz t cdv write d(a2) burst write d(a2+1) read q(a3) read q(a4) burst read q(a4+1) write d(a5) read q(a6) write d(a7) deselect oe t oev t oelz t oehz dont care undefined d(a5) t doh q(a4+1) d(a7) q(a6) notes 28. for this waveform zz is tied low. 29. when ce is low, ce 1 is low, ce 2 is high and ce 3 is low. when ce is high, ce 1 is high or ce 2 is low or ce 3 is high. 30. order of the burst sequence is determined by the status of the mode (0 = linear, 1 = interleaved). burst operations are opti onal.
cy7c1371d cy7c1373d document number: 38-05556 rev. *l page 28 of 37 figure 8. nop, stall and deselect cycles [31, 32, 33] switching waveforms (continued) read q(a3) 456 78910 a3 a4 a5 d(a4) 123 clk ce we cen bw [a:d] adv/ld address dq c ommand write d(a4) stall write d(a1) read q(a2) stall nop read q(a5) deselect continue deselect dont care undefined t chz a1 a2 q(a2) d(a1) q(a3) t doh q(a5) notes 31. for this waveform zz is tied low. 32. when ce is low, ce 1 is low, ce 2 is high and ce 3 is low. when ce is high, ce 1 is high or ce 2 is low or ce 3 is high. 33. the ignore clock edge or stall cycle (clock 3) illustrates cen being used to create a pause. a wr ite is not perform ed during this cycle.
cy7c1371d cy7c1373d document number: 38-05556 rev. *l page 29 of 37 figure 9. zz mode timing [34, 35] switching waveforms (continued) t zz i supply clk zz t zzrec a ll inputs (except zz) dont care i ddzz t zzi t rzzi outputs (q) high-z deselect or read only notes 34. device must be deselected when entering zz mode. see truth t able for all possible signal conditions to deselect the device. 35. dqs are in high z when exiting zz sleep mode.
cy7c1371d cy7c1373d document number: 38-05556 rev. *l page 30 of 37 ordering code definitions ordering information cypress offers other versions of this type of product in many different configurati ons and features. the below table contains o nly the list of parts that are currently available. for a comple te listing of all options, visit the cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products or contact your local sales representative. cypress maintains a worldwide network of offices, solution center s, manufacturer's representatives and dist ributors. to find the office closest to you, visit us at http://www.cypress.com/go/datasheet/offices . speed (mhz) ordering code package diagram part and package type operating range 133 cy7c1371d-133bgc 51-85115 119-ball bga (14 22 2.4 mm) commercial cy7c1373d-133bzi 51-85180 165-ball fbga (13 15 1.4 mm) lndustrial cy7c1371d-133axc 51-85050 100-pin tqfp (14 20 1.4 mm) pb-free commercial cy7c1373d-133axi lndustrial 100 cy7c1371d-100axc 51-85050 100-pin tqfp (14 20 1.4 mm) pb-free commercial CY7C1373D-100AXC cy7c1371d-100axi 51-85050 100-pin tqfp (14 20 1.4 mm) pb-free lndustrial temperature range: x = c or i c = commercial = 0 ? c to +70 ? c; i = industrial = ?40 ? c to +85 ? c x = pb-free; x absent = leaded package type: xx = bg or bz or a bg = 119-ball bga bz = 165-ball fpbga a = 100-pin tqfp speed grade: xxx = 133 mhz or 100 mhz process technology: d ?? 90 nm part identifier: 137x = 1371 or 1373 1371 = ft, 512 kb 36 (18 mb) 1373 = ft, 1 mb 18 (18 mb) technology code: c = cmos marketing code: 7 = sram company id: cy = cypress x c 137x d - xxx xx x cy 7
cy7c1371d cy7c1373d document number: 38-05556 rev. *l page 31 of 37 package diagrams figure 10. 100-pin tqfp (14 20 1.4 mm) a100ra package outline, 51-85050 51-85050 *d
cy7c1371d cy7c1373d document number: 38-05556 rev. *l page 32 of 37 figure 11. 119-ball pbga (14 22 2.4 mm) bg119 package outline, 51-85115 package diagrams (continued) 51-85115 *d
cy7c1371d cy7c1373d document number: 38-05556 rev. *l page 33 of 37 figure 12. 165-ball fbga (13 15 1.4 mm) bb165d /bw165d (0.5 ball diameter) package outline, 51-85180 package diagrams (continued) 51-85180 *f
cy7c1371d cy7c1373d document number: 38-05556 rev. *l page 34 of 37 acronyms document conventions units of measure acronym description bga ball grid array cmos complementary metal oxide semiconductor ce chip enable cen clock enable eia electronic industries alliance fbga fine-pitch ball grid array i/o input/output jedec joint electron devices engineering council jtag joint test action group lsb least significant bit msb most significant bit nobl no bus latency oe output enable sram static random access memory tap test access port tck test clock tdi test data input tms test mode select tdo test data output tqfp thin quad flat pack ttl transistor-transistor logic we write enable symbol unit of measure c degree celsius mhz megahertz a microampere ma milliampere mm millimeter ms millisecond mv millivolt nm nanometer ns nanosecond ? ohm % percent pf picofarad vvolt wwatt
cy7c1371d cy7c1373d document number: 38-05556 rev. *l page 35 of 37 document history page document title: cy7c1371d/cy7c1373d, 18-mbit (512 k 36/ 1 m 18) flow-through sram with nobl? architecture document number: 38-05556 rev. ecn no. submission date orig. of change description of change ** 254513 see ecn rkf new data sheet. *a 288531 see ecn syt updated features (removed 117 mhz frequency related information). updated selection guide (removed 117 mhz frequency related information). updated ieee 1149.1 serial boundary scan (jtag) (edited description for non-compliance with 1149.1). updated electrical characteristics (removed 117 mhz frequency related information). updated switching characteristics (removed 117 mhz frequency related information). updated ordering information (updated part numbers (added pb-free information for 100-pin tqfp, 119-ball bga and 165-ball fbga packages), added comment of ?pb-free bg packages availability? below the ordering information). *b 326078 see ecn pci updated pin configurations (address expansion pins/balls in the pinouts for all packages are modified according to jedec standard). updated ieee 1149.1 serial boundary scan (jtag) (updated tap instruction set (updated overview (updated description), updated extest (updated description), added extest output bus tristate )). updated electrical characteristics (updated test conditions of v ol, v oh parameters). updated thermal resistance (changed value of ? ja and ? jc parameters for 100-pin tqfp package from 31 ? c/w and 6 ? c/w to 28.66 ? c/w and 4.08 ? c/w respectively, changed value of ? ja and ? jc parameters for 119-ball bga package from 45 ? c/w and 7 ? c/w to 23.8 ? c/w and 6.2 ? c/w respectively, changed value of ? ja and ? jc parameters for 165-ball fbga package from 46 ? c/w and 3 ? c/w to 20.7 ? c/w and 4.0 ? c/w respectively). updated ordering information (updated part number s, removed comment of ?pb-free bg packages availability ? below the order ing information). *c 345117 see ecn pci changed status from preliminary to final. updated ordering information (updated part numbers). *d 416321 see ecn nxr changed address of cypress semiconductor corporation from ?3901 north first street? to ?198 champion court?. updated partial truth table for read/write (bw a of write byte a ? (dq a and dqp a ) and bw b of write byte b ? (dq b and dqp b ) has been changed from h to l). updated electrical characteristics (changed ?input load current except zz and mode? to ?input leakage current except zz and mode? in the description of i x parameter, changed the minimum value of i x parameter correpsonding to input current of mode (input = v ss ) from ?5 ? a to ?30 ? a, changed the maximum value of i x parameter correpsonding to input current of mode (input = v dd ) from 30 ? a to 5 ? a, changed the minimum value of i x parameter correpsonding to input current of zz (input = v ss ) from ?30 ? a to ?5 ? a, changed the maximum value of i x parameter correpsonding to input current of zz (input = v dd ) from 5 ? a to 30 ? a, updated note 20 (changed v ih < v dd to v ih < v dd )). updated ordering information (updated part numbers, replaced package name column with package diagram in the ordering information table).
cy7c1371d cy7c1373d document number: 38-05556 rev. *l page 36 of 37 *e 475677 see ecn vkn updated tap ac switching characteristics (changed minimum value of t th and t tl parameters from 25 ns to 20 ns, changed maximum value of t tdov parameter from 5 ns to 10 ns). updated maximum ratings (added the maximum rating for supply voltage on v ddq relative to gnd). updated ordering information (updated part numbers). *f 1274734 see ecn vkn / aesa updated switching waveforms (updated figure 8 (corrected typo in the waveform)). *g 2897120 03/22/2010 njy updated ordering information (removed inactive parts). updated package diagrams . *h 3033272 09/19/2010 njy added ordering code definitions . added acronyms and units of measure . minor edits and updated in new template. *i 3067448 10/21/2010 njy updated ordering information (updated part numbers). *j 3353119 08/24/2011 prit updated functional description (updated note as ?for best practice recommendations, refer to sram system guidelines .?). updated package diagrams (spec 51-85050 (changed revision from *c to *d)). *k 3613540 05/10/2012 prit updated functional description (removed the note ?for best practice recommendations, refer to sram system guidelines .? and its reference). updated pin configurations (updated figure 3 (removed cy7c1373d related information), updated figure 4 (removed cy7c1371d related information)). updated package diagrams (spec 51-85180 (changed revision from *c to *e)). *l 3767562 10/05/2012 prit updated package diagrams (spec 51-85115 (changed revision from *c to *d), spec 51-85180 (changed revision from *e to *f)). document history page (continued) document title: cy7c1371d/cy7c1373d, 18-mbit (512 k 36/ 1 m 18) flow-through sram with nobl? architecture document number: 38-05556 rev. ecn no. submission date orig. of change description of change
document number: 38-05556 rev. *l revised october 5, 2012 page 37 of 37 nobl and no bus latency are trademarks of cypress semiconductor corporation. zbt is a trademark of integrated device technology , inc. all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c1371d cy7c1373d ? cypress semiconductor corporation, 2004-2012. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5

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